1. Field of the Invention
This invention relates to activation of precharged SRAMs, and more particularly to self-activation of precharged SRAMS through the use of a self-timing clock generator.
2. Description of the Prior Art
The reduction of power consumption and the escalation of digital component speed are significant concerns with modern digital circuitry. This is due to significant increases in gate densities particularly with Very Large Scale Integrated Circuits (VLSI) such as Application Specific Integrated Circuits (ASICs). In order to help reduce the power density of such VLSIs/ASICs and increase speed in a digital system using Static Random Access Memory (SRAM) chips, "precharged" SRAMs may be used. A precharged Static Random Access Memory (SRAM) is a memory device which places a memory block into a low power "precharge" mode when it is not accessed, and sets precharged SRAM outputs to a known logic state while in a "precharge" mode. This power reduction has enabled SRAMs to be implemented in higher density and with smaller gates and cells. This allows the precharged SRAM to give a higher performance.
In order to precharge a precharged SRAM for reading and writing data, an activation or "precharge" signal must be received by the precharged SRAM. This signal must be present for a specified duration in order to precharge the precharged SRAM to perform data reads and writes. Precharging will be terminated when a read or write function is initiated. The precharged SRAM of the preferred embodiment has a clock input for receiving the triggering clock edge to clock memory reads and writes. The same clock input also receives the precharge signal to precharge the device. The logic state of the signal (hereinafter referred to as the precharge/clock signal) at the clock input of the precharged SRAM determines whether the device is being precharged, or is being clocked. For example, a low precharge/clock signal will precharge the device, while a low-to-high transition will clock the device to perform memory read and write functions.
In order to precharge and clock the precharged SRAM, an oscillating clock signal can be generated to directly clock and precharge the SRAM. However, by supplying a fixed frequency, fixed duty cycle clock signal to the clock input, a worst-case timing analysis must be performed to calculate the fastest clock signal that can be safely used to obtain the required precharge and clocking times. Therefore, it would be advantageous to know when a memory read or memory write has completed, so that precharging can immediately begin. Where completion of the memory cycle is known, worst case analysis would not be required for memory access times, since the "actual" time of completion of a memory read or write would be known.
The present invention reduces the time between memory reads and writes by affording a method of discerning the completion of a memory read or write cycle, which allows precharging to begin as soon as the memory read or write has completed. This is performed by initially latching the active level of a clock signal, and resetting the latch upon completion of the memory read or write. This "self-timed" clock generator therefore switches the state of the signal at the clock input to precharge mode at the earliest possible time, and therefore allows precharging of the memory device to be as long as possible before the next read or write activity. The memory device will begin precharging at an earlier time than where worst-case memory cycle times are used to initiate precharging.
Where a precharged SRAM is embedded in an Application-Specific Integrated Circuit (ASIC), it is desirable to have less than 50% duty cycles for clock signals having very high frequencies. This is because extended periods of a high logic level can cause "hot spots" in the ASIC, which can cause damage to the component. The self-timed clock generator of the present invention provides the smallest duty cycle possible, since the precharge/clock signal will drop to a low logic level as soon as the data is valid for a read or write cycle. The duty cycle reduction of the precharge/clock signal also has the effect of lowering total power consumption. The self-timing operation of the present invention also allows the minimum precharge time of the precharged SRAM to be more easily met, and allows greater system clock speeds than where precharging begins following a worst-case synchronous timing period.
A "Self-Timed Precharge Circuit" is disclosed in U.S. Pat. No. 4,638,462, by Rajeevakumar et al., issued Jan. 20, 1987. The Rajeevakumar et al. design utilizes a self-timed precharge circuit and multiple falling-edge detectors to generate the precharge signal. Activation of the precharge signal occurs when a particular word line goes from the active to the inactive state. This occurs when the memory address becomes inactive, and in turn inactivates the word line. The inactivation of the word line is detected by the word line's respective falling-edge detector, which then activates the precharge signal.
The present invention is designed to activate the precharge signal at a time prior to that of a precharge circuit of the type disclosed by Rajeevakumar et al. The present design avoids the use of a falling-edge detector for every row in a memory array. The goal of the present invention is to activate the precharge signal as soon as possible after a data access cycle has completed. Therefore, rather than wait until the address becomes inactive, the present invention has circuitry to activate the precharge signal as soon as the data is valid. The advantages of doing so were previously described, which include reducing power consumption, and potentially allowing for increased clock speeds since the active clock pulse width is minimized.
A self-timing precharge circuit is also disclosed in U.S. Pat. No. 4,914,633, by Rose et al., issued Apr. 3, 1987. This patent, entitled "Self-Timed Programmable Logic Array With Precharge Circuit", has an internal timing circuit for indicating when the output signals are valid. However, the timing circuit generates an output enabling signal a "predetermined time" later to enable downstream circuitry to use the output signals. The present invention differs from Rose et al. because this predetermined time delay is precisely what the present invention is designed to avoid. The present invention activates the precharge signal almost immediately upon completion of a data read or write cycle, and therefore is not forced to wait until the end of the address cycle.
Apart from precharge signal concerns, it is important to be able to test the memory device to ensure that precharged SRAM activity is working as designed. It is also important to be able to monitor the system in which the precharged SRAM resides for faults or for determining the current status of the system. For these cases, the present invention provides a "test enable" circuit that will disable the self-timed clock generator. This circuit also provides means for clocking the precharged SRAM with an external test clock.
The self-timing clock generator of the present invention allows the precharge signal to be activated as soon as valid data is present on the data bus. This allows a reduction of power consumption due to a longer low voltage period on the precharge/clock signal. Minimizing the logic high period for the precharge/clock signal reduces the chance of damage to the ASIC. Furthermore, the minimum precharge time is more easily met where the precharge signal is activated as soon as the read or write data is valid. This can potentially allow for increased clock speeds, and increased system speeds as the semiconductor process and technology matures and/or improves. These advantages, coupled with the ability to test the precharged SRAM, establish the novelty of the present invention.